1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an imaging apparatus.
2. Description of the Related Art
In general, shallow trench isolation (STI) is used for element isolation in a finer semiconductor integrated circuit in recent years. However, since STI is provided by digging deeply a trench in a semiconductor substrate, a crystal defect or an interface state occurs at an interface between an insulating film buried in the trench serving for element isolation and the semiconductor substrate so as to become a noise source. Therefore, regarding a CMOS image sensor, in the case where the STI is adopted as a method for element isolation of a pixel portion in parallel with a peripheral circuit, deterioration of a characteristic occurs in such a way that noises are generated at the interface between the semiconductor substrate dug and the insulating film buried. Consequently, a method, in which the amount of digging of the semiconductor substrate in an element isolation region of the pixel region is reduced so as to suppress generation of noises from an element isolation end, has been proposed as a technique for reducing deterioration of a solid-state imaging element due to noise (refer to, for example, Japanese Unexamined Patent Application Publication No. 2006-24786 and Japanese Unexamined Patent Application Publication No. 2006-93319).
However, even in the case where the above-described element isolation method is applied, in which the amount of digging for the element isolation of the pixel portion is reduced, as shown in FIG. 13 and FIG. 14, it is necessary that a hole accumulation layer 113 is formed under an element isolation region 112 of a pixel portion 111 by introducing a P-type impurity. FIG. 13 described above shows a plane layout of the pixel portion, and FIG. 14 is a sectional view showing the section of a pixel portion, taken along a line XIV-XIV shown in FIG. 13.
As a result, an effect of diffusion of the impurity of the hole accumulation layer 113 becomes significant as the pixel becomes finer, and effective channel widths of a reset transistor 114R, an amplifying transistor 114A, a selection transistor 114s are reduced because of the effect of diffusion of the P-type impurity. If the effective channel width is reduced as described above, deterioration of 1/f noise of, in particular, the amplifying transistor 114A becomes a problem.
Furthermore, it has become difficult to increase the channel width because the pixel has been made finer.
Consequently, it has become difficult to ensure the compatibility between noise reduction and a finer pixel.
Moreover, a method has been proposed, in which a conductor for voltage application is buried in the STI in order to bring the interface between an insulating film for element isolation and a semiconductor substrate into a hole accumulation state, for the purpose of suppressing generation of noises in an element isolation region of an STI structure (refer to, for example, Japanese Unexamined Patent Application Publication No. 2006-120804).
In the method in which the conductor for voltage application is buried into the above-described SDI, it is necessary that a conductor for applying a negative voltage is buried in the element isolation region. At that time, it is necessary that the conductor is buried into the element isolation region around, in particular, the selection transistor and the amplifying transistor of the pixel region in such a way as to avoid becoming electrically continuous with polysilicon serving as a gate electrode of the transistor. However, it is difficult to bury the conductor throughout the element isolation region of the pixel region of a fine pixel while avoiding polysilicon of the gate electrode. Consequently, regarding the purpose of suppressing deterioration of 1/f noise along with the effect of reducing the channel of the transistor of the pixel, it is difficult to obtain a deterioration suppression effect by burying the conductor.